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CUHK

CENG2010 Digital Logic Design Laboratory

Course Review By Teaching Professors


Course Reviews on CENG2010 Digital Logic Design Laboratory

Shared by Anonymous

2020-01-13

Professor: Dr Sum Kwok Wing, Anthony


Course Description
Bscis VHDL programming
Assessment
70% labs and homeworks, 30% final exam
Grading
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Teaching Skills & Others
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Shared by Anonymous

2018-08-25

Professor: LAM Tak Kei


Course Description
Simple circuit implemented by software
Assessment
3 hw 1exam
Grading
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Teaching Skills & Others
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Shared by Anonymous

2018-08-25

Professor: LAM Tak Kei


Course Description
VHDL

Concurrent statements

Sequential statements

Hierarchical Design

Sequential logic

Assessment
Lab 30%

Homework 20%

Exam 50%
Grading
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Teaching Skills & Others
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Shared by Anonymous

2018-08-25

Professor: Dr. Eden Ma


Course Description
VHDL 'basics'
Assessment
Lab- 20%

Assignment- 30%

Final- 50%
Grading
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Teaching Skills & Others
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